Chief Technology Officer (High-Speed Analog)

• THE COMPANY
• Established in early 2024, at Analogue Insight we are bridging the Analogue and Digital Worlds for Tomorrow through our Chiplet Solutions. Our core expertise lies in developing cutting-edge Chiplet technology that serves as the building block for advanced communication systems. Our Chiplets are designed to offer high performance, scalability, and integration flexibility, enabling our clients to achieve breakthroughs in computation speed, data processing, and connectivity. For more information about us, check out our website (Analogue Insight) and LinkedIn Page (Analogue Insight™: Overview | LinkedIn).

• THE ROLE
• We are seeking an exceptional Chief Technology Officer (High-Speed Analog) to lead the technical vision of Analogue Insight as we grow from a fast-moving start-up into a scale-up. As CTO, you will own the technology strategy for our electrical and photonic interconnect portfolio – 112G/224G-class SerDes, 32G/64G UCIe die-to-die PHYs, high-bandwidth memory interfaces, data converters (ADC/DAC) and optical I/O – and drive it across our customer programmes and product roadmap. You will lead the CTO Office, act as the company's senior technical voice with customers, partners, foundries and investors, and build deep links between Analogue Insight and leading universities and research institutes.
• This role is ideal for a recognised leader in high-speed analog and mixed-signal design, with strong academic standing and strong ties to industry. We particularly welcome candidates with a professorship or senior research background who want to see their work reach customer silicon.
• Location: Fully remote, ideally based in the UK, Europe, Armenia, India, Canada or the US.
• Reporting to: CEO, as a member of the executive team.
• Hiring Manager: Christian Borelli, Founder, CEO & CPO.

KEY RESPONSIBILITIES:

• Technology Vision & Strategy: Define and own Analogue Insight's long-term technology vision for electrical and photonic interconnect, grounded in first-principles engineering and aligned with market needs, customer roadmaps and the company's growth plans.

• IP & Product Roadmap: Translate the strategy into a clear multi-year IP roadmap – next-generation SerDes, UCIe die-to-die links, high-bandwidth memory interfaces, data converters and optical I/O – prioritising investment, tape-outs and advanced-node choices, and owning technical risk mitigation, with the CEO and executive team.

• Architecture & Technical Authority: Act as the final technical authority on architecture, circuit approaches and design methodology, setting aggressive performance, power, area and robustness targets, and leading technical reviews across architecture, analog/mixed-signal, digital, layout and validation.

• Hardest Technical Problems: Personally drive resolution of the most challenging circuit and system issues through first-principles analysis, modelling, simulation and silicon-based investigation.

• Design Closure & Silicon Success: Ensure robust design closure – post-layout verification, performance optimisation and silicon-to-model correlation – so that our IP is first-time-right in customer silicon.

• CTO Office & Technical Leadership: Build and lead the CTO Office and the technical leadership team, mentoring senior and principal engineers, raising the technical bar and shaping our technical career track.

• Research & Innovation: Lead advanced R&D and technology exploration, driving architectural innovation in high-speed analog, mixed-signal and photonic circuits, and growing a strong patent and publication portfolio.

• Academic & Research Partnerships: Leverage your network to build and lead partnerships with top universities and research institutes, including joint research programmes, funded projects, PhD and post-doc collaborations, and talent pipelines.

• Customer & Industry Engagement: Serve as the senior technical voice of the company with customers, foundries, EDA vendors, standards bodies and ecosystem partners, supporting key wins and strategic engagements.

• Investor & Board Support: Represent the technology vision to investors, advisors and the board, and support technical due diligence for fundraising, grants and potential acquisitions.

• Engineering Excellence: Promote rigorous engineering practices, design quality and knowledge sharing, and champion design automation, simulation automation and AI-assisted design to scale productivity and quality.

• WHAT WE’RE LOOKING FOR
• Must-have Technical skills:

• Ph.D. in Electrical Engineering or a related field, with a focus on high-speed analog/mixed-signal circuit design

• 15+ years of combined industry and/or academic experience in high-speed analog design, including senior technical leadership roles

• World-class expertise in at least one of: high-speed wireline transceivers (SerDes, die-to-die links), clocking and PLLs, or high-speed data converters – with a strong system-level view across the full link

• Strong understanding of advanced CMOS (FinFET and beyond), packaging and chiplet integration, and the interaction between circuits, channels and systems

• Proven track record of taking complex designs from architecture to successful silicon

• Strong academic and industry standing, evidenced by publications at leading venues (e.g. ISSCC, VLSI, JSSC, CICC), patents and invited talks

• An established network across leading universities, research institutes and the semiconductor industry

• Experience building and leading high-performing technical teams, ideally including distributed or remote teams

Nice-to-have:

• Current or past professorship or senior research position at a leading university

• Deep, hands-on expertise in one or more of the following circuit areas:

• Fractional-N PLLs, LC-VCOs, DTC/TDC, multi-modulus dividers

• Phase interpolators, injection-locked oscillators, multi-phase clock generation

• High-speed time-interleaved DACs and line drivers

• TIAs, CTLEs, PGAs and other high-bandwidth amplifiers

• Time-interleaved SAR ADCs and track-and-hold circuits

• Bandgaps, LDOs, temperature sensors and other precision/support circuits

• Experience in photonic or optical interconnect (e.g. TIAs, drivers, co-packaged optics)

• Experience with circuit modelling, simulation automation, optimisation and silicon-to-model correlation

• Involvement in standards bodies or consortia (e.g. UCIe, JEDEC, OIF, IEEE)

• Experience securing and leading funded research programmes and industry–academia collaborations

• Start-up or scale-up experience, including working with investors and boards

Soft & Professional Skills:

• Inspiring, clear communication in professional English – able to engage engineers, customers, academics and investors alike

• Strategic thinker who is also comfortable going deep into technical details

• Collaborative, feedback-oriented leadership style that builds trust across a remote team

• Demonstrated ability to mentor and grow senior engineers and future technical leaders

• Strong ownership, reliability, and follow-through

• High level of integrity and professionalism in representing the company and handling sensitive information

• We are looking for a technical leader who combines deep circuit-design expertise with architectural thinking, research vision and hands-on execution to solve the hardest problems in next-generation high-speed connectivity – and who can build a team that does the same.

• OUR CULTURE
• We’re a fully remote team of around 25 people distributed across the UK, Armenia, Italy, the US, Estonia, India, and beyond. We believe great talent is everywhere!

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• Our values are our north star:We Grow Together, We Win Together. Excellence Builds Relationships. Trust Is Our Currency. Results Matter, but People Create Them.

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• Connected, even remotely:We invest intentionally in staying connected through regular all-hands, 1:1s, technical reviews, and informal coffee chats, so collaboration feels natural and human despite the distance.

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• High ownership, real impact:Everyone contributes directly to customer-facing IP. Your work doesn’t disappear into layers of management – it ships.

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• How we work:We move fast but thoughtfully, communicate openly, and balance autonomy with support. Technical decisions are debated openly and grounded in data, trade-offs, and first-principles thinking.

WHY JOIN US:

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• Remote-first flexibility – work from anywhere, with flexible hours

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• Equipment & setup – we’ll provide the tools you need to succeed

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• High-impact projects – design real analog IP used in customer silicon

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• Supportive team culture – a dedicated manager and a team of colleagues ready to help

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• Competitive, transparent compensation– adjusted for your location and engagement model

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• Learning & growth – AI–DLP sessions, technical deep dives, and peer-led knowledge sharing that build both technical depth and system-level perspective

RECRUITMENT PROCESS:

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• Founder Call (30 min) – mutual introduction and interest alignment

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• Technical Interview(90 min) – fundamentals, reasoning, and problem-solving

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• Second Technical Interview (60 min) – another deep-dive into specific topics, which might include a presentation that we'll let you know about in advance

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• Senior Management Discussion (60 min) – another deep-dive into specific topics with our Senior Management Team

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• HR & Culture Call (45 min)–values, collaboration style, and ways of working

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• Offer &

Next Steps– we send the offer and kick off the onboarding process.

Disclaimer: This is our standard process for most roles. For more senior, specialized, or higher-authority positions, we reserve the right to amend or tailor these steps as we see fit.

If you don’t meet every requirement but feel excited about the role, apply anyway. We value curiosity, integrity, and potential as much as experience.

Originally posted on Himalayas