Verification Engineer

We’re seeking a Verification Engineer to contribute to the validation of advanced chip designs. You’ll help create and maintain UVM environments, write tests, and ensure functional coverage for high-performance silicon products. The role involves close collaboration across architecture, design, and circuit teams.

Responsibilities

• �� Understand chip and subsystem architecture.
• �� Develop, maintain, and extend UVM-based verification environments.
• �� Write test plans, test cases, and sequences for block- and chip-level verification.
• �� Debug design issues based on architectural specifications.
• �� Work with design and architecture teams to meet quality and schedule goals.

Qualifications

• �� BSEE/MSEE or equivalent in Electrical Engineering, Computer Science, or a related field.
• �� Proficient in Verilog/SystemVerilog and UVM.
• �� Comfortable working in Linux and with industry-standard EDA tools.
• �� Solid grasp of verification methodologies and design processes.
• �� Excellent teamwork and communication skills.
• �� Experience with functional and code coverage analysis.

Preferred / Plus

• �� Strong problem-solving and analytical skills.
• Originally posted on Himalayas